在日常例行性的交通中，從A處到B處，已經習慣某條行車路線後，如果臨時想去C處買個小東西，在前往途中，一不留神就會在必須轉彎的街口繼續沿舊路線前進。個人將此種行為稱之為慣性的迷失。對於許多人來說，慣性的迷失在日常生活中經常發生，大多無傷大雅。但是如果發生在工程案件和商業案件中，則會造成相當程度的損失，小則浪費幾天的人力物力，大則危及企業根本。
After having driven from place A to place B daily for years, most people are gradually used to going to and fro along one or two routes. Occasionally, we may forget to make a turn at the right intersection when we want to buy something at the middle way, place C. I call this mistake to be “lost in inertial” that happens in daily life from time to time for many people. Most of them are harmless. However, when it happens in engineering cases and/or business cases, it will result in damages to some extent. The loss may be only a few of manpower and material resources, may be a huge damage to the enterprise.
廿幾年前在工研院材料所微結構分析實驗室工作。某天接到一個半導體元件良率的案子，客戶送來二組表面長有磊晶層的矽晶圓，經過相同的製程，用A組晶圓製作的元件的良率都低於50%，而用B組晶圓製作的元件的良率則高於95%。客戶要鑑定A組晶圓內的磊晶層是否有造成低良率的缺陷。利用TEM進行樣品的橫截面分析。第一天，完成A組晶圓的TEM試片製作，在TEM中，觀察到矽磊晶層和矽基板的界面有幾個數奈米大小的空孔。第二天，完成B組晶圓的TEM試片製作，但是在TEM中找不到矽磊晶層和矽基板的界面。估計沒有磨對位置，第三天，再製作第二個B組晶圓的TEM試片，仍然找不到矽磊晶層和矽基板的界面。
I received a case of yield issue when I worked at microanalysis laboratory in MRL, ITRI more than twenty years ago. Semiconductor devices made by two sets of epi Si wafers had big different yield under same processes. Set A had yield less than 50%, while set B had yield more than 95%. My mission was to characterize what kind of defect(s) in the epi layer. I used TEM to analyze the cross-section structure of these samples. A TEM specimen of A was made at the first working day, and several nano voids were observed at the interface of epi layer and Si substrate. A TEM specimen of B was made at the second day, but nothing except Si substrate was observed. With the assumption of grinding and polishing wrong place, a second TEM specimen of B was made at the third day. Unfortunately, there was still only one single crystal observed in TEM. The interface of epi Si layer and the Si substrate as observed in sample A was not found.
第四天，預定交付資料的前一天，完成第三個B組晶圓的TEM試片，在TEM中搜尋一遍後，仍然找不到矽磊晶層和矽基板的界面。此時已經晚上11點。疲乏的我到室外走走散心，順便思考今晚是否要研磨第四個B試片，以及如何向客戶提出延期的說詞。沈思中，忽然靈光一閃，摻雜濃度等級的矽同質磊晶層和矽基板之間，正常狀況下，本來就看不到界面。一直想要看到磊晶層和矽基板的界面是因為A試片和以往分析異質磊晶層樣品的經驗造成的慣性思維。
The third TEM specimen of sample B was prepared and checked in the TEM at the fourth day, one day before the deadline. It was around 11:00pm, and there was still no solid data of sample B to deliver. Walked out TEM laboratory to take a rest and thought what was wrong with the TEM sample preparation of sample B as well as how to ask the customer to delay one or two days. During meditation, something came to my mind – nothing is correct. The interface of homogeneous epitaxial layer and the substrate is invisible when the epitaxial layer is well grown. I had been trapped in the inertial of previous knowledge from analyzing heterogenous epitaxial layers and sample A for all these days.
